An integrated circuit is a complete electronic circuit, containing transistors, diodes, resistors, and capacitors, along with their interconnecting electrical conductors, e.g., input/output (I/O) lines, contained entirely within a single chip of silicon. Integrated circuits continue to decrease in size, and the circuits they contain continue to increase in complexity. This increases the chances of defective chips resulting from a failed element or a defective conductor.
One way to reduce semiconductor scrap is to provide redundant elements on the integrated circuits. That way, if a primary element is defective a redundant element can be substituted in its place. One area which can benefit from the use of redundancy is with I/O lines of, for example, a memory circuit. Typical memory circuits comprise millions of equivalent memory cells arranged in addressable rows and columns. Modern memory blocks can include as many as 128 or more pair of I/O lines accessing a four (4) mega-bit block of memory. If one or more of these pairs of I/O lines is inoperable, then usable memory space becomes un-accessible.
Early techniques to ameliorate this situation included global re-routing to another location on or off the memory circuit chip. Global re-routing is achieved by using a replacement pair of I/O lines to address a replacement portion of memory. Replacing the defective I/O pair typically comprises opening fuse-type circuits to `program` a redundant I/O pair to respond. However, the replacement I/O and the replacement portion of memory require chip space. The cost of the chip space required by global re-routing was acceptable when I/O lines addressed a smaller number of columns. Now, however, providing additional memory blocks at other locations on or off the chip is very costly. Additionally, the timing between addressing sequences must be adjusted for the re-routing delay. This slows the operation of the memory. Thus, the global re-routing scheme requires circuitry which adversely effects the available real estate and slows the operation of the memory.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for circuits and methods to replace inoperative I/O lines without consuming valuable chip space or creating an operating time penalty.